Non-volatile memory device and method for fabricating the same

ABSTRACT

A method for fabricating a non-volatile memory device, the method includes alternately stacking inter-layer dielectric layers and sacrificial layers over a substrate, etching the inter-layer dielectric layers and the sacrificial layers to form trenches to expose a surface of the substrate, etching the inter-layer dielectric layers exposed by the trenches to a predetermined thickness, forming junction layers over etched portions of the inter-layer dielectric layers, and burying a layer for a channel within the trenches in which the junction layers have been formed to form a channel.

CROSS-REFERENCES TO RELATED APPLICATIONS

The present application claims priority of Korean Patent ApplicationNos. 10-2009-0052351 and 10-2010-0018724, filed on Jun. 12, 2009, andMar. 2, 2010, respectively, which are incorporated herein by referencein their entirety.

BACKGROUND OF THE INVENTION

Exemplary embodiments of the present invention relate to a non-volatilememory device and a method for fabricating the same, and moreparticularly, to a non-volatile memory device having a three-dimensionalstructure and a vertical channel structure.

A non-volatile memory device retains data even when power isinterrupted. As a memory device having a two-dimensional structure inwhich memory cells are arranged on a silicon substrate in a single layerreaches a limit in improving the integration density of the memorydevice, a non-volatile memory device having a three-dimensionalstructure in which memory cells are vertically stacked on a siliconsubstrate has been proposed.

A method for fabricating a conventional non-volatile memory devicehaving a three-dimensional structure will be described below in detailwith reference to FIG. 1.

FIG. 1 is a cross-sectional view illustrating a conventionalnon-volatile memory device having a three-dimensional structure.Specifically, FIG. 1 illustrates a non-volatile memory device having athree-dimensional structure and a vertical channel structure.

Referring to FIG. 1, the conventional non-volatile memory device havingthe vertical channel structure includes a lower select transistor (LST),a plurality of memory cells (MC) and an upper select transistor (UST)sequentially stacked above a substrate 10 along a channel verticallyprotruding from the substrate 10. Thus, a string is vertically arrangedon the substrate 10.

Also, the conventional non-volatile memory device includes a commonsource region doped with an N-type impurity in the substrate 10. Aplurality of strings composing a memory block are connected to thecommon source region in parallel. Specifically, a channel doped with anN-type impurity is connected to the common source region doped with theN-type impurity.

A method for fabricating the conventional non-volatile memory devicehaving the three-dimensional structure will be described below indetail.

A source region is formed by doping an impurity into the substrate 10. Aplurality of inter-layer dielectric layers 11 and a plurality ofconductive layers 12 for gate electrodes are alternately formed on thesubstrate 10 in which the source region is formed.

The inter-layer dielectric layers 11 and the conductive layers 12 forgate electrodes are selectively etched to form a trench which exposesthe surface of the substrate 10, and an insulation layer is formedinside of the trench. For example, when the lower select transistor andthe upper select transistor are formed, a gate insulation layer 13A isformed on the inner wall of the trench. When the memory cells areformed, a charge blocking layer, a charge trap layer, and a tunnelinsulation layer 13B are sequentially formed on the inner wall of thetrench.

The trench having the gate insulation layer 13A or the charge blockinglayer, the charge trap layer, and the tunnel insulation layer 13B isfilled with a layer for a channel to form a channel (CH). Thus, a lowerselect transistor (LST), a plurality of memory cells (MC) and an upperselect transistor (UST) are sequentially formed over the substrate 10along the channel CH vertically protruding from the substrate 10.

However, according to the method for fabricating the conventionalnon-volatile memory device, it is impossible to fabricate a non-volatilememory device having the memory cells operating in an enhancement-modedue to the limitations of the fabrication processes.

In the conventional non-volatile memory device having thethree-dimensional structure, the memory cells stacked along the channelprotrude vertically from the substrate 10. Herein, the channel is formedby etching the inter-layer dielectric layers 11 and the conductivelayers 12 to form the trench, and filling the trench with the layer fora channel. Thus, it is impossible to form a junction, i.e., source/drainregion, in the channel between the memory cells.

In the conventional non-volatile memory device, the source region dopedwith the N-type impurities is formed in the substrate 10, and thechannel doped with the N-type impurities forms the memory cellsoperating in a depletion mode.

Meanwhile, the memory cells operating in the depletion mode processelimination operations by providing holes through a gate induced drainleakage (GIDL) effect in the source region of the lower selecttransistor. If an insufficient amount of holes are provided, the speedof the elimination operations is lowered. Specifically, since the stringis vertically arranged on the substrate 10, the length of the channel isincreased, and the supply of the holes becomes difficult. Thus, thespeed of the elimination operations is degraded. As a result, theperformance of the non-volatile memory device is reduced.

SUMMARY OF THE INVENTION

Exemplary embodiments of the present invention are directed to anon-volatile memory device having a three-dimensional structure whichincludes a memory cell operating in an enhancement-mode, and a method offabricating the memory devices.

In accordance with an exemplary embodiment of the present invention, anon-volatile memory device includes inter-layer dielectric layers andgate electrodes alternately stacked over a substrate, channels passingthrough the inter-layer dielectric layers and the gate electrodes andprotruding from the substrate, and junction layers disposed between thechannels and the inter-layer dielectric layers.

In accordance with another exemplary embodiment of the presentinvention, a method for fabricating a non-volatile memory deviceincludes alternately stacking inter-layer dielectric layers andsacrificial layers over a substrate, etching the inter-layer dielectriclayers and the sacrificial layers to form trenches to expose the surfaceof the substrate, etching the inter-layer dielectric layers exposed bythe trenches to a predetermined thickness, forming junction layers overthe etched portions of the inter-layer dielectric layers, and burying alayer for a channel within the trenches in which the junction layers areformed to form a channel.

In accordance with still another exemplary embodiment of the presentinvention, a method for fabricating a non-volatile memory deviceincludes forming a well region over a substrate, forming a common sourceregion within the well region, alternately stacking inter-layerdielectric layers and conductive layers over the substrate having thecommon source region, etching the inter-layer dielectric layers and theconductive layers to form a trench to expose the surface of thesubstrate, forming a pickup region over the well region by doping animpurity into the substrate exposed by the trench, and burying a layerfor a channel within the trench to form a channel.

In accordance with yet another exemplary embodiment of the presentinvention, a non-volatile memory device includes memory cells stackedalong a channel vertically protruding from a substrate, a well regionarranged in the substrate, a common source region arranged within thewell region, and a pickup region arranged in the substrate to connectthe channel to the well region.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional view illustrating a conventionalnon-volatile memory device having a three-dimensional structure.

FIGS. 2A to 2F are cross-sectional views illustrating a method forfabricating a non-volatile memory device having a three-dimensionalstructure in accordance with a first exemplary embodiment of the presentinvention.

FIGS. 3A to 3D are cross-sectional views illustrating a method forfabricating a non-volatile memory device having a three-dimensionalstructure in accordance with a second exemplary embodiment of thepresent invention.

FIG. 4 is a diagram illustrating an operation of the non-volatile memorydevice having a three-dimensional structure in accordance with anexemplary embodiment of the present invention.

FIGS. 5A and 5B illustrate a non-volatile memory device having athree-dimensional structure in accordance with a third exemplaryembodiment of the present invention.

FIGS. 6A to 6E are cross-sectional views illustrating a method forfabricating a non-volatile memory device having a three-dimensionalstructure in accordance with the third exemplary embodiment of thepresent invention.

DESCRIPTION OF EXEMPLARY EMBODIMENTS

Exemplary embodiments of the present invention will be described belowin more detail with reference to the accompanying drawings. The presentinvention may, however, be embodied in different forms and should not beconstrued as being limited to the embodiments set forth herein. Rather,these embodiments are provided so that this disclosure will be thoroughand complete, and will fully convey the scope of the present inventionto those skilled in the art. Throughout the disclosure, like referencenumerals refer to like parts throughout the various figures andembodiments of the present invention.

The drawings are not necessarily to scale and in some instances,proportions may have been exaggerated in order to clearly illustratefeatures of the embodiments. When a first layer is referred to as being“on” a second layer or “on” a substrate, it not only refers to a casewhere the first layer is formed directly on the second layer or thesubstrate but also a case where a third layer exists between the firstlayer and the second layer or the substrate.

FIGS. 2A to 2F are cross-sectional views illustrating a method forfabricating a non-volatile memory device having a three-dimensionalstructure in accordance with a first embodiment of the presentinvention. For convenience, a lower select transistor and an upperselect transistor are not illustrated, and FIGS. 2A to 2F focus on aprocess of forming a plurality of memory cells.

Referring to FIG. 2A, a plurality of inter-layer dielectric layers 21and a plurality of sacrificial layers 22 are alternately formed on asubstrate 20. The inter-layer dielectric layers 21 serve to separate aplurality of memory cells stacked along a channel formed by thesubsequent processes. The inter-layer dielectric layers 21 may be formedof an oxide layer or a nitride layer.

The width of a junction layer formed by the subsequent processes isdetermined by the thickness of the inter-layer dielectric layers 21.Thus, the thickness of the inter-layer dielectric layers 21 may bedetermined in consideration of the width of the junction layer. Forexample, in order to increase the width of the junction layer, thethickness of the inter-layer dielectric layers 21 should be increased.

The sacrificial layers 22 serve to secure regions where a chargeblocking layer, a charge trap layer, and a tunnel insulation layer and agate electrode may be formed by the subsequent processes. Thesacrificial layers 22 may be formed of a material having a high etchselectivity with respect to the inter-layer dielectric layers 21. Forexample, when the inter-layer dielectric layers 21 may be formed of anoxide layer, the sacrificial layers 22 may be formed of a nitride layer.Also, when the inter-layer dielectric layers 21 may be formed of anitride layer, the sacrificial layers 22 may be formed of an oxidelayer.

A plurality of trenches T1 for channels are formed by etching theinter-layer dielectric layers 21 and the sacrificial layers 22. Herein,the plurality of trenches T1 may be cylinders and may be arranged apredetermined distance apart from each other. The reference designation“W1” represents a first width of the trenches T1.

Referring to FIG. 2B, the inter-layer dielectric layers 21 exposed bythe trenches T1 may be etched to a second width W2. The referencedesignation “21A” represents etched inter-layer dielectric layers, andthe reference designation “T1” represents trenches extended through theetch process. Herein, the etch process of the inter-layer dielectriclayers 21 to the second width W2 secures an area where the junctionlayer may be formed through the subsequent processes. The second widthW2, that is, the etched width of the inter-layer dielectric layers 21,may be determined in consideration of the width of the junction layer.For example, the inter-layer dielectric layers 21 may be etched to thesame thickness as the final width of the junction layer in theembodiments of the present invention. The etch process of theinter-layer dielectric layers 21 may include a wet etch process.

Referring to FIG. 2C, a first material layer for the junction 23 may beformed over a bottom portion and an inner portion of the extendedtrenches T1′ while the etched portions of the etched inter-layerdielectric layers 21A are buried. The first material layer for thejunction 23 may serve to form a junction, i.e., the source/drain regionsof the plurality of memory cells stacked along the channel. The firstmaterial layer for the junction 23 may include a polysilicon layer dopedwith an N-type impurity. The doping concentration of the impurity may bein a range of from approximately 1E10/cm² to approximately 1E15/cm².

Also, the first material layer for the junction 23 may be formed with athickness to sufficiently bury the etched portions of the etchedinter-layer dielectric layers 21A.

Referring to FIG. 2D, a portion of the first material layer for thejunction 23 may be removed, except for the first material layer for thejunction 23 formed within the etched portions of the etched inter-layerdielectric layers 21A. Thus, junction layers 23A may be formed withinthe etched portions of the etched inter-layer dielectric layers 21A, andthe junction layers 23A may be separated from each other through aremoval process.

Referring to FIG. 2E, a layer for the channel may be formed in trenchesincluding the junction layers 23A to form a plurality of channelsprotruding from the substrate 20. Herein, the layer for the channel maybe a polysilicon layer doped with a P-type impurity.

The etched inter-layer dielectric layers 21A and the sacrificial layers22 disposed between the plurality of channels may be etched to form atrench T2 for removing the sacrificial layers 22. Herein, the trench T2for removing the sacrificial layers 22 may be a line-type trench, andmay have a sufficient depth to expose all sides of the sacrificiallayers 22.

The sacrificial layers 22 exposed by the trench T2 may be removed toexpose channels spaced a predetermined distance apart from each other.The removing process of the sacrificial layers 22 may be performed undera condition having a high etch selectivity with respect to the etchedinter-layer dielectric layers 21A. For example, when the sacrificiallayers 22 may be formed of an oxide layer and the etched inter-layerdielectric layers 21A may be formed of a nitride layer, HF or BOE may beused to remove the sacrificial layers 22. In this case, the etchselectivity of the sacrificial layers 22 with respect to the etchedinter-layer dielectric layers 21A is greater than approximately 50:1.

Also, when the sacrificial layers 22 may be formed of a nitride layerand the etched inter-layer dielectric layers 21A may be formed of anoxide layer, phosphoric acid may be used to remove the sacrificiallayers 22. In this case, the etch selectivity of the sacrificial layers22 with respect to the etched inter-layer dielectric layers 21A isgreater than approximately 20:1.

Here, all of the sacrificial layers 22 may be removed or a portion ofthe sacrificial layers 22A located between the channels may remainduring the removing process. FIG. 2E shows a case of a portion of thesacrificial layers 22A located between the channels remaining.

Referring to FIG. 2F, a charge blocking layer, a charge trap layer, anda tunnel insulation layer may be formed over the resultant structure inwhich a portion of the sacrificial layers 22 has been removed. In FIG.2F, the charge blocking layer, the charge trap layer, and the tunnelinsulation layer are illustrated as a single layer. Referencedesignation “24” represents the layer including the charge blockinglayer, the charge trap layer, and the tunnel insulation layer.

The charge blocking layer, the charge trap layer, and the tunnelinsulation layer 24 may be formed along the removed region of thesacrificial layers 22 with a predetermined thickness such that a middleregion of the removed region of the sacrificial layers 22 may remainopen.

Then, a gate electrode 25 may be buried in the removed region of thesacrificial layers 22. That is, the gate electrode 25 may be formedwithin the open middle layer after the charge blocking layer, the chargetrap layer, and the tunnel insulation layer 24 have been formed.Specifically, the gate electrode 25 may be formed within the open middleregion by forming a conductive layer over the resultant structureincluding the charge blocking layer, the charge trap layer, and thetunnel insulation layer 24, and performing an etch-back process onto theconductive layer.

As a result, the plurality of memory cells may be stacked along thechannels, and the memory cells may include the channel CH, the chargeblocking layer, the charge trap layer, and the tunnel insulation layer24, and the gate electrode 25.

As described above, the non-volatile memory device having thethree-dimensional structure in accordance with the first embodiment ofthe present invention may include the etched inter-layer dielectriclayers 21A and the gate electrodes 25 alternatively stacked over thesubstrate 20, the channel CH protruding from the substrate 20 and formedthrough the etched inter-layer dielectric layers 21A and the gateelectrodes 25, junction layers 23A surrounding an outer surfaces of thechannel a predetermined distance apart from each other and disposedbetween the channel and the etched inter-layer dielectric layers 21A,and the memory cells stacked along the channel.

The memory cells may further include the charge blocking layer, thecharge trap layer, and the tunnel insulation layer 24 disposed betweenthe channel and the gate electrodes 25. The non-volatile memory devicehaving the three-dimensional structure may further include the remainingsacrificial layer 22A located between the channels arranged in apredetermined direction and formed as the same layer as the gateelectrodes 25. Also, the memory cells may be configured to operate in anenhancement-mode by the N-type junction layers 23A formed on both sideof the channel.

FIGS. 3A to 3D are cross-sectional views illustrating a method forfabricating a non-volatile memory device having a three-dimensionalstructure in accordance with a second embodiment of the presentinvention. Details of elements corresponding to those of the firstembodiment have been omitted for the sake of brevity.

As shown in FIG. 3A, a plurality of inter-layer dielectric layers 31 anda plurality of sacrificial layers 32 may be alternately formed on asubstrate 30. A plurality of trenches T3 for channels may be formed byetching the inter-layer dielectric layers 31 and the sacrificial layers32. The reference designation “W3” represents a third width of thetrenches T3.

According to the second embodiment of the present invention, the thirdwidth W3 may be determined in consideration of the subsequent processeswhen the trenches T3 for the channels are formed, since the third widthW3 of the trenches T3 is extended through the subsequent processes.

Referring to FIG. 3B, the inter-layer dielectric layers 31 exposed bythe trenches T3 may be etched to a fourth width W4. The fourth width,that is, the etched width of the inter-layer dielectric layers, may begreater than a final width of a junction layer in a range of fromapproximately 1% to approximately 20%. That is, the inter-layerdielectric layers 31 may be over-etched. The reference designation “31A”represents etched inter-layer dielectric layers, and “T3” representstrenches extended by the etch process.

Referring to FIG. 3C, a second material layer for the junction 33 may beformed over a bottom portion and an inner portion of the extendedtrenches T3′ while the over-etched portions of the etched inter-layerdielectric layers 31A are buried. The second material layer for thejunction 33 may serve to form a junction, i.e., source/drain regions ofthe plurality of memory cells stacked along the channel. The secondmaterial layer for the junction 33 may include a polysilicon layer dopedwith an N-type impurity. The doping concentration of the impurity may bein a range of from approximately 1E10/cm² to approximately 1E15/cm².

Also, the second material layer for the junction 33 may be formed with athickness to sufficiently bury the over-etched portions of the etchedinter-layer dielectric layers 31A.

Referring to FIG. 3D, portions of the second material layer for thejunction 33 formed over a bottom portion and an inner portion of each ofthe extended trenches T3′, portions of the second material layer for thejunction 33 formed within the over-etched portions of the etchedinter-layer dielectric layers 31A, and portions of sacrificial layers 32may be removed to form a plurality of junction layers 33A.

That is, the second material layer for the junction 33 may be etched toa width obtaining by subtracting a final width W5 of the junction layers33A from a width of the second material layer for the junction 33burying the over-etched portions of the etched inter-layer dielectriclayers 31A. The junction layers 33A have a fifth width W5, and the thirdwidth W3 of the trenches T3 may be extended to a sixth width W6. Thus,junction layers 33A may be completely separated from each other throughthe removal process.

Subsequent processes for forming a channel and a gate electrode may beperformed to form the non-volatile memory device having athree-dimensional structure in the same manner as that of the firstembodiment of the present invention.

FIG. 4 is a diagram illustrating an operation of the non-volatile memorydevice having a three-dimensional structure in accordance with anembodiment of the present invention. FIG. 4 is a magnified view of ‘A’of FIG. 2F.

As shown in FIG. 4, the non-volatile memory device having thethree-dimensional structure in accordance with an embodiment of thepresent invention may include N-type junction layers 23A formed on bothsides and a P-type channel CH in a plurality of the memory cells.

The junction layers 23A may serve as source/drain regions. Since N-typeimpurities may be doped in the junction layers 23A, sufficient electronsmay be provided during the program operation of the memory cell. Also,since P-type impurities may be doped in the channel, sufficient holesmay be provided during the elimination operation of the memory cell.Therefore, the enhancement-mode operation of the memory cells ispossible.

FIGS. 5A and 5B illustrate a non-volatile memory device having athree-dimensional structure in accordance with a third embodiment of thepresent invention.

FIG. 5A illustrates a cross-sectional view of a vertical channel typenon-volatile memory device having a three-dimensional structure inaccordance with a third embodiment of the present invention.

As shown in FIG. 5A, the non-volatile memory device may include a lowerselect transistor (LST), a plurality of memory cells (MC) and an upperselect transistor (UST) sequentially stacked above a substrate 50 alonga channel vertically protruding from the substrate 50. Thus, a string isvertically arranged on the substrate 50.

Also, the substrate 50 may include a well region A, a common sourceregion B and a pickup region C in order to form memory cells operated inan enhancement-mode. The common source region B and the pickup region Cmay be formed within the well region A.

The pickup region C may connect the well region A and the channel CH,and the pickup region C may be formed by selectively doping impuritiesinto the substrate 50 having the common source region B. For example, amaterial layer may be formed over a substrate, and a trench may beformed by etching the material layer to expose surfaces of thesubstrate. The pickup region C may then be formed by doping impuritiesinto the exposed surfaces of the substrate disposed on the lower part ofthe trench. The impurities may be doped after forming a spacer on aninner wall of the trench.

FIG. 5B illustrates a perspective view of a substrate structure having awell region A, a common source region B and a pickup region C.

As shown in FIG. 5B, the well region A and the common source region Bmay be formed within the substrate 50; a plurality of pickup regions Cmay be formed a predetermined distance apart from each other to connectthe well region A to the channels CH of the string ST.

A width W7 of the pickup region C may be smaller than a width W8 of thechannel CH. Thus, a portion of the channel CH may be electricallyconnected to the common source region B and the rest of the channel CHmay be connected to the well region A through the pickup region C. Forexample, when a pillar-type channel is formed, the edge of thepillar-type channel may be connected to the common source region B, andthe middle of the channel may be electrically connected to the wellregion A through the pickup region C.

Consequently, the vertical channel non-volatile memory device havingmemory cells operated in an enhancement-mode may be fabricated.

FIGS. 6A to 6E are cross-sectional views illustrating a method forfabricating a non-volatile memory device having a three-dimensionalstructure in accordance with the third embodiment of the presentinvention.

As shown in FIG. 6A, a first conductive-type well region A may be formedby doping a first conductive-type impurity into a substrate 50. A secondconductive-type common source region B may be formed by doping a secondconductive-type impurity into the substrate 50 having the firstconductive-type well region A.

Herein, the first conductive-type impurity and the secondconductive-type impurity have different conductive characteristics. Forexample, the first conductive-type may be a P type while the secondconductive-type may be an N type. Thus, the well region A and the commonsource region B, having a different conductive-type from that of thewell region A, may be formed in the substrate 50.

As shown in FIG. 6B, a plurality of inter-layer dielectric layers 51 anda conductive layer 52 for a gate electrode may be alternately formed onthe substrate 50 in which the well region A and the common source regionB are formed. In FIG. 6B, a first inter-layer dielectric layer, theconductive layer for the gate electrode, and a second inter-layerdielectric layer are shown to extend from a lower select transistor.

The inter-layer dielectric layers 51 and the conductive layer 52 for thegate electrode may be selectively etched to form a trench to expose thesurface of the substrate 50, and a gate insulation layer 53A and aspacer 54A may be sequentially formed on an inner wall of the trench.

The spacer 54A may be formed to secure an overlap region between asource region of the lower select transistor and the common sourceregion B. The spacer 54A may be formed of a nitride layer, a carbonlayer or a conductive layer. When the spacer 54A is formed of theconductive layer, the spacer 54A may be formed of the same material as achannel layer which is to be formed by a subsequent process. The spacer54A may be formed of a polysilicon layer.

A first material layer for the gate insulation layer and a secondmaterial layer for the spacer may be formed over the resultant structurehaving the trench; the surface of the substrate 50 may be exposed by anetch-back process. Since the etch-back process may be performed afterthe first material layer for the gate insulation layer and the secondmaterial layer for the spacer have been formed, a loss of the firstmaterial layer for the gate insulation layer may be prevented. Also, thespacer 54A may be formed after the gate insulation layer 53A is formed.

Herein, the surface of the substrate 50 exposed by the etch-back processmay be a region for a pickup region to be formed by the subsequentprocess. At this step, the second conductive-type common source region Bmay be exposed as the surface of the substrate 50.

As shown in FIG. 6C, the pickup region C may be formed in the substrate50. The pickup region C may be formed by doping the firstconductive-type impurity into the exposed substrate 50, and thus, thesecond conductive-type common source region B may be changed to a firstconductive-type pickup region C. By doping the exposed substrate 50 withthe same conductive-type impurity of the well region A, the pickupregion C may be connected to the well region A.

The pickup region C may be formed to connect a channel to the wellregion A through the common source region B. The pickup region C may beformed by various methods including an impurity doping method. Forexample, the pickup region C may be formed by etching the common sourceregion B exposed by the trench to expose the well region, and fillingthe first conductive-type material layer within the etched region.

Since the spacer 54A is formed on an inner wall of the trench, a widthW7 of the pickup region C may be smaller than the width W8 of thechannel. As described above, the channel may be electrically inconnected to the well region A by forming the pickup region C; thesource region of the lower select transistor and the common sourceregion B may be overlapped by adjusting the width W7 of the pickupregion C. A width of the overlapped region may be adjusted by the widthof the spacer 54A.

As shown in FIG. 6D, a first conductive-type layer for the channel fillsthe trench, and a first conductive-type channel 55A may be formed. Thefirst conductive-type channel 55A may be connected to the well region Athrough the pickup region C. That is, the channel 55A may be formed withthe same conductive-type as that of the well region A, and thus, thechannel 55A may be electrically connected to the well region A throughthe pickup region C.

Herein, the layer for the channel may be formed of a polysilicon layer.When the spacer 54A is formed of polysilicon, the spacer 54A may serveas the channel. However, the spacer 54A may be formed of a nitride layeror a carbon layer; the layer for the channel may be filled in the trenchafter the spacer 54A has been removed.

Also, when the layer for the channel is filled in the trench, thesource/drain regions of the lower select transistors may be formed byperforming a gas doping process. For example, the source/drain regionsmay be formed by selectively doping the second conductive-type impurityinside the channel 55A on both sides of each inter-layer dielectriclayer 51. The source/drain regions may have the same conductivecharacteristics as that of the common source region B.

The source/drain regions of the lower select transistors may be formedinside the channel 55A on both sides of each inter-layer dielectriclayer 51. The source region S may overlap the common source region B.Thus, the source regions S of the lower select transistors included in aplurality of strings composing a memory block may be connected to thecommon source region B, the lower select transistors operating in anenhancement-mode.

Although the source/drain regions may not be formed separately, thelower select transistors may be operated by using a fringe field. Thatis, a gate bias having a predetermined level may be applied to the gateelectrode of a lower select transistor, a junction is turned on, andthus, the lower select transistor may be operated.

As shown in FIG. 6E, a plurality of memory cells MC and upper selecttransistors UST are formed over the resultant structure having the lowerselect transistors LST. Hereinafter, processes for forming memory cellswill be described.

A plurality of inter-layer dielectric layers 51 and a plurality ofconductive layers 52 for gate electrodes may be alternately formed overthe resultant structure in which the lower select transistors LST areformed. The inter-layer dielectric layers 51 and the conductive layers52 for the gate electrodes may be selectively etched to form a trenchwhich exposes the channel 55A of the lower select transistors.

A charge blocking layer, a charge trap layer, and a tunnel insulationlayer 53B may be sequentially formed on the inner wall of the trench.Also, a spacer 54B may be formed over the charge blocking layer, thecharge trap layer, and the tunnel insulation layer 53B to protect thecharge blocking layer, the charge trap layer, and the tunnel insulationlayer 53B during the subsequent etch-back process.

Then, a channel 55B may be formed by filling the trench with a layer forthe channel. The memory cells stacked along the channel 55B are formed,and the channel vertically protrudes from the substrate 50. Thesource/drain regions of the memory cells may be formed by performing thegas doping process in the same manner as that of the lower selecttransistors.

Furthermore, the upper select transistors UST may be formed over theresultant structure in which the memory cells are formed. Processes forforming the upper select transistors may be the same as those of thelower select transistors.

As a result, a vertical channel type non-volatile memory device having athree-dimensional structure including the lower select transistors,memory cells and the upper select transistors configured to operate inthe enhancement-mode may be formed. Therefore, the performance of thememory device may be improved by increasing the speed of the programoperations and the elimination operations.

Referring to FIGS. 6A to 6E, according an impurity doping method to formthe pickup region C, the P-type well region A, the N-type type commonsource region B and the P-type pickup region C may be formed in thesubstrate 50, and the P-type channel CH may be connected to the P-typewell region A through the P-type pickup region C. That is, the firstconductive-type may be the P-type while a second conductive-type may bethe N-type. However, the conductive-type may be changed based on thedesign. In the present invention, the channel CH and the well region Ahaving the same conductive-type may be connected through the pickupregion C.

In accordance with the embodiments of the present invention,source/drain regions, i.e., junction regions may be in a plurality ofmemory cells stacked along a channel which protrudes vertically from asubstrate. Accordingly, a non-volatile memory device having athree-dimensional structure which includes memory cells operating in anenhancement-mode may be provided.

Furthermore, in accordance with the embodiments of the presentinvention, since a well region, a common source region and a pickupregion may be formed in a substrate, a channel may be connected to thewell region through the pickup region. Specifically, a firstconductive-type well region, a second conductive-type common sourceregion and a first conductive-type pickup region may be formed, and afirst conductive-type channel may be connected to the firstconductive-type well region through the first conductive-type pickupregion. Thus, a non-volatile memory device having a three-dimensionalstructure which includes memory cells operating in an enhancement-modemay be provided.

While the present invention has been described with respect to thespecific embodiments, it will be apparent to those skilled in the artthat various changes and modifications may be made without departingfrom the spirit and scope of the invention as defined by the followingclaims.

1. A non-volatile memory device comprising: a plurality of inter-layerdielectric layers and a plurality of gate electrodes alternately stackedover a substrate; a plurality of channels passing through the pluralityof inter-layer dielectric layers and the plurality of gate electrodesand protruding from the substrate; and a plurality of junction layersdisposed between the plurality of channels and the plurality ofinter-layer dielectric layers.
 2. The non-volatile memory device ofclaim 1, further comprising: a charge blocking layer, a charge traplayer, and a tunnel insulation layer disposed between the plurality ofchannels and the plurality of gate electrodes.
 3. The non-volatilememory device of claim 1, wherein a plurality of memory cells includedin the non-volatile memory device are configured to operate in anenhancement-mode.
 4. The non-volatile memory device of claim 1, whereinthe plurality of channels are doped with a P-type impurity, and theplurality of junction layers are doped with an N-type impurity.
 5. Thenon-volatile memory device of claim 4, wherein a doping concentration ofthe N-type impurity is in a range of from approximately 1E10/cm² toapproximately 1E15/cm².
 6. A method for fabricating a non-volatilememory device, the method comprising: alternately stacking a pluralityof inter-layer dielectric layers and a plurality of sacrificial layersover a substrate; etching the plurality of inter-layer dielectric layersand the plurality of sacrificial layers to form a plurality of trenchesto expose a surface of the substrate; etching the inter-layer dielectriclayers exposed by the plurality of trenches to a predeterminedthickness; forming a plurality of junction layers over etched portionsof the inter-layer dielectric layers; and burying a layer within theplurality of trenches in which the plurality of junction layers havebeen formed to form a plurality of channels.
 7. The method of claim 6,wherein the plurality of inter-layer dielectric layers are formed of anoxide layer and the plurality of sacrificial layers are formed of anitride layer, or the plurality of inter-layer dielectric layers areformed of a nitride layer and the plurality of sacrificial layers areformed of an oxide layer.
 8. The method of claim 6, wherein the etchingof the plurality of inter-layer dielectric layers to the predeterminedthickness includes performing a wet etch process.
 9. The method of claim6, wherein the forming of the plurality of junction layers includes:forming a material layer for a junction over a bottom portion and aninner portion of the plurality of trenches while the etched portions ofthe plurality of inter-layer dielectric layers are buried; and removinga portion of the material layer for the junction except for the materiallayer for the junction formed within the etched portions of the etchedplurality of inter-layer dielectric layers to separate each of thejunction layers.
 10. The method of claim 6, wherein the etching of theplurality of inter-layer dielectric layers to the predeterminedthickness includes over-etching the plurality of inter-layer dielectriclayers to be greater than a final width of the plurality of junctionlayers in a range of from approximately 1% to approximately 20%.
 11. Themethod of claim 10, wherein the forming of the plurality of junctionlayers includes: forming a material layer for a junction over a bottomportion and an inner portion of the plurality of trenches while theover-etched portions of the plurality of inter-layer dielectric layersare buried; and removing portions of the material layer for the junctionformed over the bottom portion and the inner portion of the plurality oftrenches, portions of the material layer for the junction formed withinthe over-etched portions of the plurality of inter-layer dielectriclayers, and portions of the plurality of sacrificial layers beingconfigured to separate each of the junction layers and to determine afinal width of the junction layers.
 12. The method of claim 6, furthercomprising: forming a trench for removing the plurality of sacrificiallayers by partially etching the etched plurality of inter-layerdielectric layers and the plurality of sacrificial layers between theplurality of channels; removing the plurality of sacrificial layersexposed by the trench for removing the plurality of sacrificial layers;forming a charge blocking layer, a charge trap layer, and a tunnelinsulation layer over a resultant structure in which the plurality ofsacrificial layers have been removed; and forming gate electrodes overthe resultant structure in which the charge blocking layer, the chargetrap layer, and the tunnel insulation layer have been formed.
 13. Themethod of claim 12, wherein the trench for removing the plurality ofsacrificial layers includes a line-type trench.
 14. A method forfabricating a non-volatile memory device, the method comprising: forminga well region over a substrate; forming a common source region withinthe well region; alternately stacking a plurality of inter-layerdielectric layers and a plurality of conductive layers over thesubstrate having the common source region; etching the plurality ofinter-layer dielectric layers and the plurality of conductive layers toform a trench to expose a surface of the substrate; forming a pickupregion over the well region by doping an impurity into the substrateexposed by the trench; and burying a layer for a channel within thetrench to form a channel.
 15. The method of claim 14, further comprisingforming source/drain regions inside the channel on both sides of each ofthe plurality of inter-layer dielectric layers.
 16. The method of claim14, further comprising forming a charge blocking layer, a charge traplayer, and a tunnel insulation layer on an inner wall of the trench. 17.The method of claim 16, further comprising forming a spacer over thecharge blocking layer, the charge trap layer, and the tunnel insulationlayer.
 18. The method of claim 17, wherein forming the spacer comprisesforming one of a nitride layer, a carbon layer, and a conductive layer.19. The method of claim 18, wherein forming the conductive layerincludes forming a polysilicon layer.
 20. The method of claim 14,wherein a width of the pickup region is formed to be smaller than awidth of the channel.
 21. The method of claim 14, wherein the wellregion is formed to have a same conductive-type as that of the pickupregion and the channel.
 22. The method of claim 21, wherein the wellregion is formed to have a different conductive-type than that of thecommon source region.
 23. The method of claim 21, further comprisingelectrically connecting the channel to the well region through thepickup region.
 24. The method of claim 14, wherein a plurality of memorycells included in the non-volatile memory device are configured tooperate in an enhancement-mode.
 25. A non-volatile memory devicecomprising: a plurality of memory cells stacked along a channelvertically protruding from a substrate; a well region arranged in thesubstrate; a common source region arranged within the well region; and apickup region arranged in the substrate to connect the channel to thewell region.
 26. The non-volatile memory device of claim 25, wherein theplurality of memory cells are configured to operate in anenhancement-mode.
 27. The non-volatile memory device of claim 25,wherein a width of the pickup region is smaller than a width of thechannel.
 28. The non-volatile memory device of claim 25, wherein aconductive-type of the well region is the same as that of the pickupregion and the channel.
 29. The non-volatile memory device of claim 28,wherein the conductive-type of the well region is different from that ofthe common source region.
 30. The non-volatile memory device of claim25, wherein the channel is electrically connected to the well regionthrough the pickup region.